I. Field of the Disclosure
The field of the disclosure relates to dual-string digital-to-analog converters (DACs), and particularly to interconnections and switching of primary and secondary voltage dividers provided therein.
II. Background
A digital-to-analog converter (DAC) is a device that converts digital codes to representative analog signals. For example, the converted analog signals may be recreations of native analog signals previously converted into the digital codes by an analog-to-digital converter (ADC). A common use of ADCs and DACs is converting audio and video signals used in media devices (e.g. televisions, cell phones, MP3 players, etc.) from analog sign representations to digital signal representations, or vice versa.
One type of DAC is a dual-string DAC. A dual resistor string DAC (also referred to as “dual-string DAC”) requires fewer resistors and switches to convert digital codes into analog signal representations as compared to single resistor string DACs. A dual-string DAC includes a first resistor string that generates a coarse conversion of a digital code. A second resistor string of the dual-string DAC generates a finer interpolation of the coarse conversion of the digital code received from the first resistor string to provide an output voltage providing an analog signal representation of the digital code. For example, if a dual-string DAC is configured to convert six (6) bit binary digital codes into sixty-four (64) unique conversions (i.e., 26 conversions), each resistor string of the dual-string DAC could each include eight (8) resistors for a total of sixteen (16) resistors, as opposed to providing sixty-four (64) resistors in a single-string DAC.
For example, FIG. 1 illustrates an exemplary dual-string DAC 10 (referred to herein as “DAC 10”). The DAC 10 functions by applying a received input voltage Vin across a primary voltage divider circuit 12, referred to herein as “primary voltage divider 12.” The primary voltage divider 12 provides coarse voltage (i.e., analog signal) values by dividing the input voltage Vin across a plurality of primary resistors R(0)-R(N−1) in a primary resistor string 14 at selected resistor node pairs Nr(0)-Nr(N) at nodes between the primary resistors R(0)-R(N−1). For example, if N equals sixteen (16), this means the number of primary resistors R(0)-R(N−1) provided in the primary voltage divider 12 totals sixteen (16). In this example, the primary voltage divider 12 provides sixteen (16) unique divided primary voltages selectable by four (4) binary bits of a digital code provided to the primary voltage divider 12 for conversion. For example, the bits of a digital DAC input code 15 (hereinafter “DAC input code 15”) are used to select the primary voltages, as illustrated in FIG. 1. In this example, the most significant bits N of the DAC input code 15 are used to select the primary voltages. A coarse divided primary voltage value is selected by a primary switch unit 16 that selects a pair of primary switches U(0)-U(2N−1) to select a selected resistor node pair Nr among a plurality of selected resistor node pairs Nr(0) to Nr(N) in the primary resistor string 14 to select one of the divided primary voltages as a selected coarse divided primary voltage Vp. This selected coarse divided primary voltage Vp is applied across a secondary voltage divider circuit 18, referred to herein as “secondary voltage divider 18.”
With continuing reference to FIG. 1, the secondary voltage divider 18 is provided in the DAC 10 and configured to further divide the selected coarse divided primary voltage Vp into a plurality of finer secondary voltages. In this regard, the secondary voltage divider 18 comprises a plurality of secondary resistors Rs(0)-Rs(Y−1) to form a secondary resistor string 20. Similar to the primary resistor string 14, the secondary resistor string 20 divides the applied primary voltage from the primary voltage divider 12 into finer, interpolated secondary voltages. As the primary voltage is applied across the secondary resistor string 20, a secondary output voltage Vout is selected by a secondary voltage divider switch 22. For example, if Y equals thirty-two (32), meaning the number of secondary resistors Rs(0)-Rs(Y−1) provided in the secondary voltage divider 18 totals thirty-two (32), the secondary voltage divider 18 provides thirty-two (32) unique divided secondary voltages. The thirty-two (32) unique divided secondary voltages are selectable by five (5) binary digital code bits provided to the secondary voltage divider 18. For example, the bits of the DAC input code 15 used to select the secondary voltages may comprise the least significant five (5) bits (LSB) of the DAC input code 15. A finer, interpolated secondary voltage value is selected by the secondary voltage divider switch 22 by selecting a resistor node Nsr. The selected resistor node Nsr is selected from among resistor nodes Nsr(0)-Nsr(Y) in the secondary resistor string 20 to provide a final, secondary output voltage Vout representing the converted DAC input code 15.
When the DAC 10 in FIG. 1 converts the DAC input code 15 into the secondary output voltage Vout, the DAC 10 transfer function remains monotonic throughout the range of possible digital codes. The DAC 10 being montonic in this example means that the DAC 10 will generate a secondary output voltage Vout that increases (or stays constant) or decreases (or stays constant) for a given incremental change in the DAC input code 15. Montonicity in the DAC 10 may be desired if it is desired for the DAC 10 convert digital codes to representative analog signals in a linear fashion. The DAC 10 is designed to be monotonic to be linear. More specifically, the DAC 10 in FIG. 1 being monotonic means the selected coarse divided primary voltage Vp and the secondary output voltage Vout of the DAC 10 either increases or stays constant for a monotonically increasing DAC input code 15, or decreases or stays constant for a monotonically decreasing DAC input code 15. For example, as the DAC input code 15 increases in value, the selected coarse divided primary voltage Vp and the secondary output voltage Vout increase or remain constant (i.e., not decrease) for the DAC 10. Likewise, as the DAC input code 15 decreases in value, the selected coarse divided primary voltage Vp and the secondary output voltage Vout decrease or remain constant (i.e., not increase) for the DAC 10.
With continuing reference to FIG. 1, primary switches U(0)-U(2N−1) are provided in the primary switch unit 16 of the DAC 10. The primary switches U(0)-U(2N−1) are configured to be controllably opened and closed to select the desired selected resistor node pair 49 among the plurality of selected resistor node pairs Nr(0)-Nr(N). Selecting the desired selected resistor node pair among the selected resistor node pairs Nr(0)-Nr(N) selects the selected coarse divided primary voltage Vp in the primary voltage divider 12 to be applied to the secondary resistor string 20. The primary switches U(0)-U(2N−1) are provided in pairs for each selected resistor node to maintain monotonicity in the DAC 10. For example, if the voltage across the selected resistor node pair Nr(2) and Nr(3) in the primary voltage divider 12 is selected to be applied across the secondary resistor string 20, primary switch U(3) is selected to couple Nr(2) to a positive input terminal 24I of the secondary resistor string 20. Switch U(6) is selected to couple Nr(3) to a negative input terminal 26I of the secondary voltage string 20. If the most significant bits (MSB) of the DAC input code 15 increments, causing the voltage across selected resistor node pair Nr(3) and Nr(4) to be selected, the primary switch U(5) must be selected instead of primary switch U(6). Primary switch U(5) must be selected to couple selected resistor node pair Nr(3) to the positive terminal 24I of the secondary resistor string 20. Otherwise, if primary switch U(6) were continued to be selected, Nr(3) would remain coupled to the negative terminal 26I of the secondary resistor string 20 of the secondary resistor string 20, thus causing the selected coarse divided primary voltage Vp in the primary voltage divider 12 to not be applied incrementally, in kind, with the increment in the DAC input code 15 across the secondary resistor string 20. Thus, the DAC 10 would not be monotonic. Thus in summary, if the primary switches U(0)-U(2N−1) are not provided in pairs for each selected resistor node Nr(0)-Nr(N), polarity changes (e.g., polarity flips) will occur in the selected coarse divided primary voltage Vp applied across the secondary resistor string 20. Monotonicity would be lost as a result.